Dear all,

As the Chair of the IEEE EPS Germany Chapter, together with Prof. Bernhard Wunderle from TU Chemnitz, we would like to invite you to a lecture by IEEE EPS Distinguished Lecturer John Lau. The seminar will be held as a hybrid event.

If you would like to attend in person, please come to TU Chemnitz (Zentrales Hörsaal- und Seminargebäude Raum: 2/N012, Reichenhainer Str. 90, 09126 Chemnitz) on Monday, October 28th at 13:00. The seminar will begin at 13:30 and conclude at 15:15.

If you prefer to join online, please find the link in the attached flyer.

Below you can find details about seminar: 

Chiplet Design and Heterogeneous Integration Packaging

John H Lau, Unimicron Technology Corporation

 Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have been generated lots of tractions lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. In this lecture, the following topics will be covered.

• System-on-Chip (SoC)
• Why Chiplet Design?
• Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split
• Chip partition and Heterogeneous Integration
• Chip split and Heterogeneous Integration
• Advantages and Disadvantages
• Communication between Chiplets (e.g., Bridges)
• Bridge Embedded in Build-up Package Substrate
• Bridge Embedded in Fan-Out EMC with RDLs
• UCIe
• Hybrid Bonding Bridge
• Chiplet Design and Heterogeneous Integration Packaging - Multiple System and Heterogeneous Integration
• Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration)
• Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration)
• Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration)
• Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration)
• Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration)
• Advanced Packaging Driving by Artificial Intelligent
• Co-Packaged optics
• Summary

Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging

Trends in Chiplet Design and Heterogeneous Integration Packaging

Who Should Attend?

If you (students, engineers, and managers) are involved with any aspect of the electronics industry, you should attend this course. It is equally suited for R&D professionals and scientists. The lectures are based on the publications by many distinguish authors and the books by the lecturer.

Lecturer Bio

John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 520 peer-reviewed papers (375 are the principal investigator), 52 issued and pending US patents (30 are the principal inventor), and 23 textbooks (all are the first author), e.g., Chiplet Design and Heterogeneous Integration Packaging (525 pages, Springer, 2023). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.

Please let me know if you have any questions,

Przemyslaw Gromala

IEEE EPS Germany Chapter Chair