Dear Member,

As part of IEEE Bangalore Section-EDS Bangalore Chapter Collaboration following 2 Webinars are arranged. You are invited to attend the webinars. 

Date/Time: June 9, 7-8PM

Title: The Future of World Electronics and Possible Roles India Can Play by Prof. Mayank Shrivasatava, DESE, IISc

Abstract: Like petroleum, electronics has become a key driver for major economies in the world. For instance, at the commercial front, China has (recently) become the biggest exporter of electronics/semiconductor products in the world. Taiwan’s major business is in Semiconductors, which is one of the key drivers of their economy. Similarly, India’s electronics import is at the verge of exceeding its oil import. At the strategic front, often the technological capabilities are driven by electronic / semiconductor technologies available in-house. In this context, India has attempted several times, in last two decades, to catch the bus in terms of setting-up a silicon CMOS foundry, which can cater to India’s commercial, strategic and scientific needs. For all practical reasons, if India attempts to catch-up the west in technologies having very high obsolescence rate, India may not be able to take a lead in future. In this context, the question is, “How India can take a lead – at the international front - in Semiconductor R&D, leading to commercial and strategic independence”? Speaker of this talk believes that for India to become a leader, India must jump the technology roadmap and rather than only catching-up on the established technologies, invests pro-actively on disruptive technologies projected for future. This talk will be pitched with the vision and belief highlighted above, while discussing 5 key disruptive technologies, which can be game changers as far as future of electronics is concerned.     

Register at: 

https://ieeemeetings.webex.com/ieeemeetings/onstage/g.php?MTID=eac697df59991dfd7b0eb198eb8171326

Date/Time: June 11, 7-8PM

Title: Defect Assisted Atomic Orbital Overlap Engineering in 2D Materials Resulting in Record High Performance Transistors by Prof. Mayank Shrivasatava, DESE, IISc

Abstract: In this talk, different techniques to strengthen atomic orbital overlap are presented to engineer metal – graphene / metal - TMD contacts, while highlighting relevance of atomic orbital overlap engineering in the contact region of 2D materials. For example, the fundamental understanding of contact’s quantum chemistry and role of sp-hybridized carbon atoms has resulted in record low contact resistance for CVD graphene when compared with the best reported results till date for CVD as well as epitaxial graphene – metal contacts. Similarly, a universal approach, using the principle of atomic orbital overlap engineering, was discovered to engineer metal - TMD contacts. Role of contact engineering in terms of reaching graphene FET’s intrinsic limits with scalability will be discussed in detail. Finally, results on record high (i) graphene transistor and (ii) 2D TMD transistor performance will be discussed and demonstrated as a result of engineered contacts and process technology.  

Register at: 

https://ieeemeetings.webex.com/ieeemeetings/onstage/g.php?MTID=ea77642c6298c55a69188c69dd64033f5

Bio: Prof. Mayank Shrivastava received his PhD degree from Indian Institute of Technology Bombay (2010). For his PhD work he received excellence in research award for his PhD thesis and industrial impact award from IIT Bombay in 2010. He is among the first recipients of Indian section of American TR35 award (2010) and the first Indian to receive IEEE EDS Early Career Award (2015). Besides, he is an IEEE Senior Member and has received several other national awards and honors of high repute, like National Academy of Sciences, India, (NASI) Young Scientist Platinum Jubilee Award – 2018; Indian National Academy of Science (INSA) Young Scientist Award - 2018; Indian National Academy of Engineering (INAE) Innovator Entrepreneur Award 2018 (Special commendation); Indian National Academy of Engineering (INAE) Young Engineer Award - 2017; INAE Young Associate (since 2017); Indian Academy of Sciences (IASc), Young Associate, 2018 – 2023; Department of Electronics & Information Technology (DeitY), Young Faculty Fellowship.  He has received best paper awards from several international conferences like Intel Corporation Asia academic forum; VLSI design conference and EOSESD Symposium. Prof. Shrivastava’s current research deals with experimentation, design and modeling of beyond CMOS devices using Graphene and TMDCs, wide bandgap material-based power semiconductor devices and ESD reliability in advanced and beyond CMOS nodes. He had held visiting positions in Infineon Technologies, Munich, Germany from April 2008 to October 2008 and again in May 2010 to July 2010. He worked for Infineon Technologies, East Fishkill, NY, USA; IBM Microelectronics, Burlington, VT, USA; Intel Mobile Communications, Hopewell Junction, NY, USA; and Intel Corp., Mobile and Communications Group, Munich, Germany between 2010 and 2013. He joined Indian Institute of Science as a faculty member in year 2013 where he is currently working as an Associate Professor. Prof. Shrivastava has over 125 peer reviewed international publications and 47 patents. 

Webinars are free to attend. However Registration is mandatory.

Kindly Join the Webinar 5-10 mins before so that we can start the program on time.