Title: VLSI Design for Excellence(DFX) for Autonomous Vehicles

Venue: NMREC, Ghatkesar      Date: 21 December 2018    Time: 11AM to 12.00PM.

Abstract: Very Large Scale Integration (VLSI) methodology and manufacturing process has grown rapidly in the last few decades enabling us to design and encapsulate billions of transistors in single mammoth chips. Design For Excellence (DFX) such as – Design for Functional Safety (DFS), Design For Testability (DFT), and Design For Manufacturing (DFM) – encompass several aspects of VLSI methodology and manufacturing process towards realizing these System-on-Chips (SoCs)

Autonomous Vehicles (AV) are beginning to surface up in the streets of USA, Europe, & Asia. These self-driving vehicles are equipped with a variety of sensors such as Computer Vision, RADAR – RAdio Detection And Ranging, LIDAR – LIght Detection And Ranging, SONAR – SOund Navigation And Ranging, GPS – Global Positioning System to perceive the surroundings, obstructions, traffic signs, and coordinates. Real-time processing and decision-making for these AVs are implemented by powerful Graphic Processing Units (GPUs) based System-on-Chips (SoCs). VLSI DFX plays a very important role in realizing these GPU based SoCs from design concept-to-tapeout.

In this talk, we will introduce design features of AV vehicles, and the GPU based SoCs that forms the cockpit for these AV vehicles. We will delve into VLSI methodology aspects into designing these GPUs and SoCs. In particular, we will cover a few DFX aspects such as DFS, DFT, and DFM. We will also introduce the International Standards Organization (ISO) mandate for Functional Safety in AVs and the needs for its compliance.

Gopal’s Bio-Data: Rajagopalan (Gopal) Srinivasan currently manages functional safety engineering aspects for Graphics Processing Units (GPUs) at Nvidia Corporation in Santa Clara, USA. Prior to the current assignment, he led the Design for Testability (DFT) aspects for all Nvidia Central Processing Units (CPUs) and their associated Tegra System-on-Chips (SoCs). Gopal has more than 25 years of extensive technical design and management experience having worked for various organizations –

•          Intel Corporation in Folsom, California (CA) & Morganville, New Jersey (NJ)
•          Lucent Bell Labs (now Nokia Labs) at Murray Hill & Princeton in NJ
•          Stanford University Network (SUN) Microsystems (now Oracle Corp.) at Menlo Park, CA.
•          Texas Instruments (TI), Bangalore

 Gopal received his

•          B. Tech in Electronics from the Indian Institute of Technology, Madras
•          M.E. in Computer Science & Communications from the IISC, Bangalore
•          M.S. & Ph.D. in Computer Engineering from the University of Southern California, Los Angeles.

Gopal has published several technical papers and articles in IEEE/ACM Conferences and Transactions. He has been in Technical Program Committees for various International Conferences and has represented Nvidia in several Technical Panels.

Brochure is available on https://drive.google.com/open?id=1KRnRP4OD_J0J0rW-K5cBKDg_MWMdXY0U

Regards
Arif Sohel,Chair, IEEE CAS/EDS Chapter, Hyderabad Section. 
Dr. Mohammed Arifuddin Sohel 
Professor and Head, Department of Electronics and Communication Engineering
Muffakham Jah College of Engineering and Technology
Banjara Hills, Hyderabad, AP. 500034
Mobile - 9885 407094