IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium is the premier international conference in the Asia-Pacific region to share the recent progress of design, modeling, simulation and measurement related to the electrical issues arising at the chip, package and system levels.

Covering the paper presentations, industry exhibitions, workshops and tutorials, EDAPS 2018 will be held at the Taj Chandigarh. The technical program of the symposium not only addresses the current technical issues but also brings out the topics on IC design, SiP/SoP packaging, EMI/EMC, EDA tools and most importantly the challenging issues in advanced 3D-IC and TSV design. For further information, please consult the website. http://www.edaps2018.org/

Call for Papers EDAPS 2018 seeks original papers describing research and innovations in all areas of electrical design of chip, package and systems for electronics application. You are invited to submit abstracts that provide non-commercial information of new developments and knowledge in these areas:

• 3 Dimensional Integrated Circuits (3D-ICs)/Through Silicon Via (TSVs)/Interposers
• Testing on 3D-IC and System-in-Package (SiP)
• Signal and thermal integrity
• Power integrity/power distribution networks (PDNs)/ground noise
• Computational electromagnetics and multi-physics methods for Signal Integrity (SI)/Power Integrity (PI)/Thermal Integrity (TI) analysis
• Thermal management design for 3D-ICs and SiP
• Design and modeling for high-speed channels and interconnects
• High speed serial links jitter budgeting
• Jitter segregation algorithms and tools
• Time/frequency domain measurement techniques
• Power supply induced jitter and transfer functions
• Nanoelectronics for 3D-ICs and SiP
• Machine Learning applied to packaging
• Active devices and circuit modeling technologies
• Electronic packages, SiP/System-on-Package (SoP)
• IC and Package Level Electromagnetic Compatibility (EMC)
• Antennas in packages (AiP)
• Radio Frequency (RF)/mm-wave and Terahertz Packages
• Miniaturized and embedded passives
• Power electronic packages
• Advanced simulation tools and Computer Aided Design (CAD)
• Substrate technology for packages and Printed Circuit Boards (PCBs)
• Electrical design of flexible devices and sensing
• 2D Materials for 3D-ICs and SiP
• 3D ICs and SiP Reliability
• Electrical design for 5G wireless communication
• Double Data Rate (DDRs) signal and power integrity considerations
• Others

The symposium will include both oral and poster sessions. In addition, a number of prominent experts will be giving keynote lectures and tutorials on areas of emerging interest. The official language is English.
The submission format is two column, three page, PDF format only.

Authors of accepted papers will be invited to submit an extended version of their manuscript for a Special Section based on EDAPS 2018 to be published in the IEEE Transactions on Components, Packaging and Manufacturing Technology (T-CPMT).

All papers should be submitted electronically in two column and three page PDF file format. All submissions must be made through EDAPS website. A Microsoft Word template is available on the symposium website. Hardcopy submission will NOT be accepted. Submitted manuscripts should be camera ready and compliant with the general standards of the IEEE, including appropriate referencing. Non-compliant manuscripts will not be considered for review.

An IEEE copyright transfer form completed with paper title, author(s) name(s) and author signatures should be submitted at the time of the paper submission. Files with scanned signatures are considered valid documents. Please visit the symposium website for updates on the paper submission.

For more information, please contact: edaps2018@emlab.illinois.edu.