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Subject: Synopsys seminar in Madrid
To: CH08839 (Spain Section Chapter, CEDA44)
Grades: Honorary, Associate Members, Members, Senior Members, Fellows, Life Members, Life Seniors, Life Fellow, Graduate Student Members, Student Members
Memberships: Active
Priority: Normal Reminder: None
Reply to: pacov@imse-cnm.csic.es Private: No
Attachments: None

 

To view complete details for this event, click here to view the announcement

Synopsys seminar in Madrid


The Spain Chapter of the IEEE Council on Electronic Design Automation (CEDA) presents a Synopsys seminar in Madrid.

The topics are:

1) Analog custom design and verification (schematic-layout-simulation-physical verification and extraction) flows and tools.

2) Digital implementation flow: Synthesis and Place&Route flows and tools.

Date and Time

Location

  • Calle Profesor José García Santesmases, 9
  • Madrid, Madrid
  • Spain 28040
  • Building: UCM: Facultad de Informática
  • Click here for Map

Contact

Registration

  • No Admission Charge
  • Starts 11 January 2018 01:00 PM
  • Ends 28 January 2018 10:00 AM
  • All times are Europe/Madrid




Spain Section Chapter, CEDA44 :
Manage your IEEE Communications Preferences
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Date: 2018-08-08 15:44:47 -0400 (Wed, 08 Aug 2018)
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