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Subject: IEEE CEDA Spain Chapter / NANOVAR Workshop
To: CH08839 (Spain Section Chapter, CEDA44)
Grades: Honorary, Associate Members, Members, Senior Members, Fellows, Life Members, Life Seniors, Life Fellow, Graduate Student Members, Student Members
Memberships: Active
Priority: Normal Reminder: None
Reply to: ceda-spain@imse-cnm.csic.es Private: No
Attachments: None

To view complete details for this event, click here to view the announcement

IEEE CEDA Spain Chapter / NANOVAR Workshop


The Spain Chapter of the IEEE Council on Electronic Design Automation (CEDA)  and the NANOVAR network present the workshop:

Title: How to survive in an unreliable world

Date: November 21, 2017

Time: 9:00 CET

Venue: Escola d'Enginyeria de Barcelona Est (EEBE), UPC Campus Diagonal-Besòs, Barcelona, Spain.

Registration: Registration required by November 15. No registration fee.

Details: Agenda included below. Click here for additional information.

Activity supported by Universitat Politècnica de Catalunya

Date and Time

Location

  • UPC Campus Diagonal-Besòs
  • Av. d'Eduard Maristany, 10-14
  • Barcelona, Cataluna
  • Spain 08930
  • Building: Escola d'Enginyeria de Barcelona Est (EEBE)
  • Click here for Map
Staticmap?size=250x200&sensor=false&zoom=14&markers=40.4530491%2c-3

Contact

Registration

  • No Admission Charge
  • Starts 04 October 2017 01:00 PM
  • Ends 15 November 2017 11:00 PM
  • All times are Europe/Madrid



Agenda

                                                                         

 

Time

 

 

Activity

 

 

Speakers

 

 

9:00-9:15

 

 

Presentation IEEE CEDA Spain Chapter and NANOVAR network

 

 

Montserrat Nafría

 

Francisco V. Fernández-José Luis Ayala

 

 

9:15-10:15

 

 

Opening lecture

 

Lifetime simulation of semiconductor circuits

 

 

Dr. Linda Milor

 

Georgia Tech

 

 

 

 

10:30-11:10

 

 

Modeling of unreliability effects in electronic devices

 

 

Dr. J. Martin-Martinez

 

UAB

 

 

11:10-11:50

 

 

Reliability in the circuit design flow: from characterization and modelling to design automation

 

 

Dr. R. Castro-López

 

IMSE-CNM

 

 

11:50-12:10

 

 

Break

 

 

 

 

 

12:10-12:50

 

 

Benefactory factors of noise and degradation in the performance of non-linear circuits

 

 

Dr. A. Rubio

 

UPC

 

 

12:50-13:30

 

 

Exploiting the variability of semiconductor fabrication process for hardware security

 

 

Dr. I. Baturone

 

IMSE-CNM

 

 

13:30-14:30

 

 

Lunch

 

 

 

 

 

14:30-15:10

 

 

Robust design based on variability monitoring 

 

 

Dr. M. Lopez Vallejo

 

UPM

 

 

15:10-15:50

 

 

Transient Radiation effects on SRAM memories

 

 

Dr. G. Torrens

 

UIB

 

 

15:50-16:10

 

 

Break

 

 

 

 

 

16:10-16:50

 

 

Why is systematic AMS-RF test not there yet?

 

 

Dr. G. Leger

 

IMSE-CNM

 

 

16:50-17:30

 

 

Test and fault diagnosis in digital circuits

 

 

Dr. R.  Rodriguez

 

UPC

 



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