Jointly Organized byIEEE

Singapore Solid-State CircuitsChapter and A*STAR IME

When: 13 – 14 June 2017

Where: A*STAR Seminar Room 3, Level 7 Innovis Tower A,

                              2 Fusionopolis Way, Singapore 138634

Time: 9:00am–5:00pm (Registration starts at 8:30am)

A NOT-TO-BE-MISSED event!

Abstract:

This short course presents some of the prominent barriers to designing energy-efficient circuits in the sub-14nm CMOS technology regime and outlines new paradigm shifts necessary in next-generation multi-core microprocessors and systems-on-chip. Emerging trends and key challenges in sub-14nm design are outlined, including (i) device and on-chip interconnect technology projections, (ii) performance, leakage and voltage scalability, (iii) special-purpose hardware accelerators and reconfigurable co-processors for compute-intensive signal processing algorithms, (iv) fine-grain power management with integrated voltage regulators, and (v) resilient circuit design to enable robust variation-tolerant operation.

Energy-efficient arithmetic and logic circuit techniques, static/dynamic supply scaling, on-die interconnect fabric circuits, ultra-low-voltage and near-threshold logic and memory circuit techniques, and multi-supply/multi-clock domain design for switching and leakage energy reduction are described. Special purpose hardware accelerators and data-path building blocks for enabling high GOPS/Watt on specialized DSP tasks such as encryption, graphics and media processing are presented. Power efficient optimization of microprocessors to span a wide operating range across high performance servers to ultra mobile SoCs, dynamic on-the fly configurability and adaptation, and circuit techniques for active/standby-mode leakage reduction with robust low-voltage operability are reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.

Course Schedule

Day 1: June 13 2017, Seminar Room 3

09:00-10:30       (1)       Energy efficient microprocessors and systems-on-chip overview

a.      Technology trends and challenges for sub-14nm design

b.      Tera-scale microprocessors and SoCs

c.   Circuit design and overview of accelerators for energy

efficient microprocessors      

10:30-10:45       Break

10:45-12:15       (2) Near-threshold and ultra-low-voltage circuit design part I

a.      Video motion estimation engine for sub-threshold operation

b.      Logic, level shifter and datapath circuits

c.      Sequential and clocking circuits

12:15-13:15       Lunch break

13:15-14:45       (3)  Near-threshold and ultra-low-voltage circuit design part II

a.      SIMD multipliers and vector permutation circuits for sub-threshold operation

b.      Memory circuits for robust ultra-low voltage operation

14:45-15:00       Break

15:00 – 16:30    (4)   On-chip interconnect scaling trends and solutions

a.      On-chip interconnect scaling challenges

b.   Network-on-chip circuit design for high performance multi-core microprocessors

Day 2: June 14 2017, Seminar Room 3

09:00-10:30       (5) Compressive sensing circuits and reconfigurable logic circuits

a.      Compressive sensing signal processing circuits for image tracking

b.      Reconfigurable logic circuits for DSP applications

c.      Near-threshold operation optimizations

d.      Silicon examples

10:30-10:45 Break

10:45-12:15       (6) Machine learning accelerator circuits for energy efficient microprocessors

a.      Variable precision arithmetic circuits

b.      K-nearest neighbor computation circuits for pattern recognition

c.    Silicon design and examples

12:15-13:15 Lunch break

13:15-14:45       (7) High performance microprocessor encryption engines

a.      Advanced Encryption Standard encryption circuit design

b.      Fully digital random number generator circuits

c.      Silicon examples

14:45-15:00 Break

15:00 – 16:30    (8) Ultra low power security circuits for IoT

a.      Nano-AES encryption accelerator circuit design

b.      Physically Unclonable Function circuit techniques

c.      Test-chip and silicon measurements

About the Instructor:

Fees:                          

SGD 900 (SGD 810)^† for regular participant

SGD 800 (SGD 720)^† for SSIA members / group registration of 2 or more from the same company *

SGD 650 (SGD 580)^†  for IEEE Member by providing Membership No. *

SGD 550 (SGD 490)^† for IEEE SSCS Member by providing Membership No. *

SGD 250 (SGD 220)^† for regular student

SGD 200 (SGD 180)^† for IEEE student members by providing Membership No. *

SGD 100 (SGD 90)^† for IEEE SSCS student members by providing Membership No. *

^† Early bird discount for registration before 13th May 2017

* mutually exclusive (choose only one, no multiple discounts)

(Hardcopy of lecture notes, lunch and refreshments will be provided)

Benefits of this Course

To learn from the industry expert &distinguished lecturer

·      Advanced IC design techniques for Energy efficient/ULV circuits and SoC in nanoscale CMOS technologies

·      Examples from recent industry designs and university research

·      Trends, challenges, opportunities in Energy efficient/ULV circuits and SoCs

Who Should Attend?

This course is designed for engineers, technical staff and students who are involved in the design of energy efficient/Ultra-low voltage circuits as well as System-on-Chips