Reminder: EDS DL - Webinar - Charge Trapping in Semiconductor Devices - Prof. Gilson Wirth : vTools eNotice

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EDS DISTINGUISHED LECTURE - Webinar - Charge Trapping in Semiconductor Devices - Prof. Gilson I Wirth

EDS DISTINGUISHED LECTURE - Webinar - Charge Trapping in Semiconductor Devices: From Device Level Modeling to Circuit Analysis - Prof. Gilson I. Wirth

Charge capture and emission by defects (traps) close to the Dielectric-Semiconductor interface is the major source of low-frequency noise in modern MOS devices. It also causes Bias Temperature Instability (BTI). The mechanisms involved in charge trapping are presented, including a critical discussion of key parameters such as trapping/de-trapping time constants and the amplitude of the fluctuations induced by single traps. A novel physics-based modeling and simulation approach for BTI, RTN and 1/f noise is presented. It allows for the derivation of analytical formulations for 1/f noise (frequency domain) and RTN (time domain) using a single modeling framework, where model parameters are the same in frequency and time domain. Low Frequency Noise (and BTI) levels can vary by several orders of magnitude in deeply scaled devices, making variability a major concern in advanced MOS technologies. To ensure proper circuit design in this scenario, it is necessary to identify the fundamental mechanisms responsible for variability in noise and BTI. Time domain analysis is relevant for the analysis of digital and mixed-signal circuits. In digital circuits, the RTN chronological statistics, especially trap occupancy switching, have direct impacts on circuit performance and reliability, as degradations like jitter of signals happen when a trap switches state. The area scaling of RTN induced jitter (phase noise) and its variability is detailed and discussed, aiming to support circuit designers in transistor sizing towards a more reliable design. The applicability of the model here presented to the evaluation of logic gates and circuits is demonstrated by case studies.