IEEE UK and Ireland Electronics Packaging and Reliability Joint Chapter

You are invited to attend the IEEE Webinar on

Advanced semiconductor packaging and the need for a workforce to support the growing semiconductor industry in the USA

Prof. Chris Bailey, Arizona State University, Tempe, Arizona, USA

Date: Friday 13^th December 2024
Time: 15:00 - 16:00
Time Zone: (UTC +00:00) Dublin, Edinburgh, Lisbon, London
Event Mode: Online via MS Teams
Free Registration: Register HERE

Organised by the IEEE UK and Ireland Electronics Packaging and Reliability Joint Chapter
and co-sponsored by the University of Greenwich, London, UK

Abstract

Advanced semiconductor packaging is now used by semiconductors companies to meet the requirements (e.g. bandwidth, latency, power, etc.) for AI and HPC applications using heterogeneous multi-chiplet architectures. These packaging techniques include flip-chip, wafer-level packaging (both fan-in and fan-out) and 3D-Heterogeneous Integration (3D-HI) and are supported by advancements in EDA/Modelling and materials characterization to address the challenges posed by the ending of Moore’s Law. 
Due to the Chips Act (USA), significant investments and initiatives are taking place across the US to support reshoring and nearshoring electronics packaging capabilities. For example, at Arizona State University (ASU) we are installing a 300mm fan-out wafer-level packaging pilot line as a core platform for advanced semiconductor packaging and heterogeneous integration. In addition to research and development activities, workforce development is a critical activity in supporting our electronics packaging industries. At ASU, we are developing and promoting stackable micro-credentials in advanced semiconductor packaging. 
This presentation will discuss developments and opportunities in advanced semiconductor packaging, the opportunities for students in the growing semiconductor workforce here in the US, and opportunities for universities and industry to collaborate in this exciting area of technology.

Presenter Bio

Professor Chris Bailey joined Arizona State University (ASU) in 2022. He is the Director of the Advanced Semiconductor Packaging Centre and a Professor in Electronics Packaging and Reliability. Before joining ASU, he was  Associate Dean for Research at the University of Greenwich, UK. He has published 400+ archival papers, and from 2020-2021 was the President of the IEEE Electronics Packaging Society. He also serves on the Heterogeneous Integration Roadmap as chapter co-chair for the Co-Design and the Modelling and Simulation Chapters.

For more information please contact:
Prof Stoyan Stoyanov, Chair IEEE UK and Ireland Electronics Packaging and Reliability Joint Chapter
E-mail: s.stoyanov@greenwich.ac.uk