BEGIN:VCALENDAR VERSION:2.0 PRODID:IEEE vTools.Events//EN CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT DTSTART:20250309T030000 TZOFFSETFROM:-0500 TZOFFSETTO:-0400 RRULE:FREQ=YEARLY;BYDAY=2SU;BYMONTH=3 TZNAME:EDT END:DAYLIGHT BEGIN:STANDARD DTSTART:20251102T010000 TZOFFSETFROM:-0400 TZOFFSETTO:-0500 RRULE:FREQ=YEARLY;BYDAY=1SU;BYMONTH=11 TZNAME:EST END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20250401T223018Z UID:820D6FA5-3E71-408B-BF1D-DE922A9BE95E DTSTART;TZID=America/New_York:20250501T120000 DTEND;TZID=America/New_York:20250501T133000 DESCRIPTION:Silicon photonics are the semiconductor integration of EIC and PIC on a silicon substrate (wafer) with complementary metal-oxide semicond uctor (CMOS) technology. On the other hand\, co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engin e (OE) which consists of photonic ICs (PIC) and the electrical engine (EE) which consists of the electronic ICs (EIC) as well as the switch ASIC (ap plication specific IC). The advantages of CPO are: (a) to reduce the lengt h of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC\ , (b) to reduce the energy required to drive the signal\, and (c) to cut t he latency which leads to better electrical performance. In the next few y ears\, we will see more implementations of a higher level of heterogeneous integration of PIC and EIC\, whether it is for performance\, form factor\ , power consumption or cost. The content of this lecture is shown below.\n \n- Silicon Photonics\n- Data Centers\n- Optical Transceivers\n- Optical E ngine (OE) and Electrical Engine (EE)\n- OBO (on-board optics)\n- NPO (nea r-board optics)\n- CPO (co-packaged optics)\n- 3D Integration of the PIC a nd EIC\n- 3D Heterogeneous Integration of PIC and EIC\n- 3D Heterogeneous Integration of ASIC Switch\, PIC and EIC\n- 3D Heterogeneous Integration o f ASIC Switch\, PIC and EIC with Bridges\n- 3D Heterogeneous Integration o f ASIC Switch\, EIC and PIC embedded in Glass-core Substrate\n- Summary an d Recommendations\n\nSpeaker(s): Dr. John H Lau\, \n\nBldg: HUB 350\, 350 Legget Dr\, Kanata\, Ontario\, Canada LOCATION:Bldg: HUB 350\, 350 Legget Dr\, Kanata\, Ontario\, Canada ORGANIZER:aabdella@ieee.org SEQUENCE:11 SUMMARY:Co-Packaged Optics – 3D Heterogeneous Integration of Photonic IC and Electronic IC URL;VALUE=URI:https://events.vtools.ieee.org/m/479253 X-ALT-DESC:Description:

\n

 \;

\n

Silicon photonics are the semiconductor integ ration of EIC and PIC on a silicon substrate (wafer) with complementary me tal-oxide semiconductor (CMOS) technology. On the other hand\, co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) and the elec trical engine (EE) which consists of the electronic ICs (EIC) as well as t he switch ASIC (application specific IC). The advantages of CPO are: (a) t o reduce the length of the electrical interface between the OE/EE (or PIC/ EIC) and the ASIC\, (b) to reduce the energy required to drive the signal\ , and (c) to cut the latency which leads to better electrical performance. In the next few years\, we will see more implementations of a higher leve l of heterogeneous integration of PIC and EIC\, whether it is for performa nce\, form factor\, power consumption or cost. The content of this lecture is shown below.

\n END:VEVENT END:VCALENDAR