IEEE CEDA Spain Chapter / NANOVAR Workshop
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IEEE CEDA Spain Chapter / NANOVAR Workshop
The Spain Chapter of the IEEE Council on Electronic Design Automation (CEDA) and the NANOVAR network present the workshop:
Title: How to survive in an unreliable world
Date: November 21, 2017
Time: 9:00 CET
Venue: Escola d'Enginyeria de Barcelona Est (EEBE), UPC Campus Diagonal-Besòs, Barcelona, Spain.
Registration: Registration required by November 15. No registration fee.
Details: Agenda included below. Click here for additional information.
Activity supported by Universitat Politècnica de Catalunya
Date and Time
- Date: 21 November 2017
- Time: 09:00 AM to 05:30 PM
- All times are Europe/Madrid
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Location
- UPC Campus Diagonal-Besòs
- Av. d'Eduard Maristany, 10-14
- Barcelona, Cataluna
- Spain 08930
- Building: Escola d'Enginyeria de Barcelona Est (EEBE)
- Click here for Map
Contact
- Email event contact
- Co-sponsored by NANOVAR Spanish Network of Excellence
Registration
- No Admission Charge
- Starts 04 October 2017 01:00 PM
- Ends 15 November 2017 11:00 PM
- All times are Europe/Madrid
Agenda
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Time
|
Activity
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Speakers
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9:00-9:15
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Presentation IEEE CEDA Spain Chapter and NANOVAR network
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Montserrat Nafría
Francisco V. Fernández-José Luis Ayala
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9:15-10:15
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Opening lecture
Lifetime simulation of semiconductor circuits
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Dr. Linda Milor
Georgia Tech
|
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10:30-11:10
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Modeling of unreliability effects in electronic devices
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Dr. J. Martin-Martinez
UAB
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11:10-11:50
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Reliability in the circuit design flow: from characterization and modelling to design automation
|
Dr. R. Castro-López
IMSE-CNM
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11:50-12:10
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Break
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|
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12:10-12:50
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Benefactory factors of noise and degradation in the performance of non-linear circuits
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Dr. A. Rubio
UPC
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12:50-13:30
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Exploiting the variability of semiconductor fabrication process for hardware security
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Dr. I. Baturone
IMSE-CNM
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13:30-14:30
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Lunch
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|
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14:30-15:10
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Robust design based on variability monitoring
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Dr. M. Lopez Vallejo
UPM
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15:10-15:50
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Transient Radiation effects on SRAM memories
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Dr. G. Torrens
UIB
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15:50-16:10
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Break
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|
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16:10-16:50
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Why is systematic AMS-RF test not there yet?
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Dr. G. Leger
IMSE-CNM
|
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16:50-17:30
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Test and fault diagnosis in digital circuits
|
Dr. R. Rodriguez
UPC
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